Electrostatic discharge (ESD) protection circuits are commonly used to protect Liquid Crystal Display (LSD) column drivers and other integrated circuits from damage due to electrostatic discharge. FIG. 1 illustrates an existing ESD protection circuit 100 for a column driver integrated circuit 104 of a typical LCD. The column driver integrated circuit 104 includes a plurality of output buffers 108-132. The output buffers 108-132 each formed by a CMOS pair of transistors are coupled to a pair of diodes. For example, the output buffer 108 includes PMOS transistor 140 and NMOS transistor 142 coupled in series between a voltage rail 134 and ground 136. A diode 144 is connected in parallel to the transistor 140 and a diode 146 is connected in parallel to the transistor 142. The diodes 144 and 146 each may be internal diodes or body diodes of the respective transistor 140 and 142 or they may by dedicated components. A pad 110 (i.e., node 110) is coupled at the common drains of the transistors 140 and 142. As is known to those skilled in the art, an electrostatic discharge (ESD) event originating outside can pass through the pads 110 into the integrated circuit. Each of the output buffers 108-132 typically have a similar configuration. The integrated circuit further has an ESD protection circuit 100 in the form of at least one (two are illustrated) clamp circuits 150 and 154 each coupled between the voltage rail 134 and ground rail 136. The clamp circuits 150 and 154 are used to limit the ESD induced voltage to a safe value to protect the integrated circuit.
FIG. 2 illustrates a circuit configuration for one of the clamp circuits, for example, clamp circuit 154, in further detail. The clamp circuit 154 generally includes an electrostatic detection circuit (EDC) 156 whose output drives the operation of a clamp transistor 220. The EDC 156 includes an R-C network 202 formed by a resistor 204 and a capacitor 208 coupled in series between the voltage rail 134 and ground rail 136 of the integrated circuit 104. The EDC 156 also includes an PMOS-type transistor 212 whose source/drain circuit is coupled in series with a resistor 216 between the voltage rail 134 and ground rail 136. The transistor 212 has a gate terminal 210 to which is coupled to a node of the R-C network 202 located between the series connected resistor 204 and capacitor 208. The clamp transistor 220 may be an NMOS-type transistor whose source/drain circuit is coupled between the voltage rail 220 and ground rail 136. The clamp transistor 220 has a gate terminal 222 which is coupled to a node 214 which is located between the drain of transistor 212 and the resistor 216.
Operation of the circuit will now be described. During an ESD event at the voltage rail 134 (i.e., a sharp rise in voltage on the rail 134), the R-C network 202 causes the gate of the transistor to go to the ground rail 136 and this turns ON the PMOS transistor 212, thereby causing current to flow through the resistor 216. As a consequence, a voltage is developed across the resistor 216 causing a rise in voltage at the gate of the clamp transistor 220. This causes the clamp transistor to turn ON very hard, essentially shorting the source/drain circuit and sinking the ESD event to the ground rail 136. As is well known to those skilled in the art, the clamp transistor 220 is a very large device and thus utilizes a significant amount of die area on the integrated circuit 104. For example, a clamp transistor may have a width between 2 mm to 15 mm.
FIG. 3 illustrates a layout of a column driver integrated circuit 300 on a rectangular die 304. The column driver integrated circuit 300 includes a plurality of output buffers 308A-308N coupled between a voltage rail 320 and ground rail 324. The output buffers 308A-308N are laid out near the periphery of the die 304. Clamp circuits 330 and 334 are each coupled between the voltage rail 320 and ground rail 324 and are placed near the center of the die 304. The clamp circuits 330 and 334 each include an EDC circuit 156 and a clamp transistor 220 (shown in FIG. 2). As illustrated in FIG. 3, the clamp circuits 330 and 334 occupy more space on the die relative to the output buffers 308A-308N because the clamp transistors require significant amount of die area.
As the size of an LCD increases, the number of output buffers increase correspondingly, thus requiring longer leads for the voltage rail 320 and ground rail 324 which degrade the performance of the clamp circuits 330 and 334. Existing solutions have proposed adding additional clamp circuits across the die, connecting power lines through the center of the die and/or adding a clamp transistor to each output buffer. FIG. 4 illustrates an existing solution implemented in a column driver 400 on a die 404. The column driver 400 includes output buffers 408A-408N each coupled between a voltage rail 420 and ground rail 424. Six clamp circuits 430, 434, 438, 442, 446 and 452 are coupled between the voltage rail 420 and ground rail 424 to provide ESD protection. Also, the voltage rail 420 and ground rail 424 are extended to pass through the center of the die. It will be appreciated that the existing solution requires additional clamp circuits which increases the die size.